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Call: Free silicon photonics fabrication for UK institutions
Third fabrication call, June 2017
As part of the EPSRC-funded CORNERSTONE project, research institutions are invited to submit mask designs to the forthcoming Silicon Photonics Multi-Project Wafer (MPW) run.
This service is offered free of charge to UK institutions, but non-UK submissions are also welcomed for a small charge: please contact cornerstone@soton.ac.ukfor pricing details.
It is important that designs conform to the following design rules to ensure clarity and correct processing. For this third call, we will process chips with a 500 nm thick silicon core on a 3 μm thick BOX (Buried OXide) layer. We will offer two etch processes: 1) shallow silicon etching of 160 nm, and 2) a deep silicon etching of 500 nm to the BOX layer. There will be no cladding layer, unless specifically requested upon mask submission.
Please see the full design rules available to download here.
The deadline for mask submission is Friday 28 July 2017.
For any queries, please contact cornerstone@soton.ac.uk
Posted by rc2c12@sot on 04 Jul 2017.